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| AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n General Description The AME9002 is AME's next generation direct drive CCFL controller. Like its cousin, the AME9001, the AME9002 controller provides a cost efficient means to drive single or multiple cold cathode fluorescent lamps (CCFL), driving 3 external MOSFETs that, in turn, drive a wirewound transformer that is coupled to the CCFL. However the AME9002 includes extra circuitry that allows for a special one second start up period wherein the voltage across the CCFL is held at a higher than normal voltage to allow older tubes (or cold tubes) a period in which they can "warm up". During this one second startup period the driving frequency is adjusted off of resonance so that the tube voltage can be controlled. As soon as the CCFL "strikes" the special start up period ends and the circuit operates in its normal mode. The AME9002 includes features such as soft start, duty cycle dimming control, dimming control polarity selection, undervoltage lockout and fault detection. It is designed to work with input voltages from 7V up to 24V. When disabled the circuit goes into a zero current mode. n Pin Configuration 24 23 22 21 20 19 18 17 16 15 14 13 AME9002 1 2 3 4 5 6 7 8 9 10 11 12 AME9002 1. VREF 2. CE 3. SSC 4. RDELTA 5. FAULTB 6. RT2 7. VSS 8. OVPH 9. OVPL 10.FCOMP 11.CSDET 12.BATTFB 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. OUTC OUTAPB OUTA VBATT BRPOL VDD CT1 FB COMP BRIGHT SSV PNP n System Block Diagram n Features l Small package: 24 pins for QSOP/ SOIC/ PDIP packages l Drives multiple tubes l Special 1 second start up mode l Automatically checks for common fault conditions l 7.0V < Vbatt < 24V l Low component count l Low Idd < 3.5mA l <1uA shutdown mode l Battery UV lockout l Brightness polarity select Controller External Components CCFL Array AME 9002 LIGHT + Resistors + Capacitors N n Applications l Notebook computers l LCD/TFT displays 1 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Pin Description Pin # 1 Pin Name VREF Pin Description Reference. Compensation point for the 3.4V internal voltage reference. Must have bypass capacitor connected here to VSS. Chip enable. When low (<0.4V) the chip is put into a low current (~0uA) shutdown mode. Blanking interval ramp. During the first cycle this pin sources 140nA. The first cycle is used to define the initial start up period, often on the order of one second. During subsequent cycles SSC sources 140mA. This is primarily used to provide a "blanking interval" at the beginning of every dimming cycle to temporarily disable the fault protection circuitry. The blanking interval is active when V(SSC) < 3.0 volts. (See application notes.) A resistor connected from this pin to VDD determines the amount that the voltage at FCOMP modulates the switching frequency. The frequency is inversely proportional to the voltage at FCOMP. 2 CE 3 SSC 4 RDELTA 5 FAULTB FAULTB pulls low when a fault is detected. A resistor from this pin to VSS sets the minimum frequency of the VCO. The voltage at this pin is 1.5V Negative supply. Connect to system ground. Over voltage protection input (HIGH). Indirectly senses the voltage at the secondary of the transformer through a resistor (or capacitor) divider. During the initial start up period, if OVPH is > 3.3V, FCOMP is driven towards VSS (increasing the frequency) and SSV is reset to zero (which decreases the duty cycle). After the initial start up period is completed the circuit will shut down if OVPH is > 3.3V. Over voltage protection input (LOW). During the initial start up period if OVPL < 2.5 volts then FCOMP is allowed to ramp up (decreasing the oscillator frequency allowing the circuit to get closer to resonance). If, during the initial start up period, OVPL > 2.5 volts then FCOMP is held at its original value (not allowed to increase so the oscillator frequency stays constant). This action is designed to hold the voltage across the CCFL constant while the CCFL "warms up". Frequency control point. Initially this pin is at VSS which yields a maximum switching frequency. Depending on the voltage at OVPL and OVPH the pin FCOMP will normally ramp upwards lowering the switching frequency towards the circuit's resonant frequency. 6 7 RT2 VSS 8 OVPH 9 OVPL 10 FCOMP 2 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Pin Description Pin # Pin Name Pin Description Current sense detect. Connect this pin to the CCFL current sense resistor divider. During the initial startup period this pin senses that the CCFL has struck when V(CSDET) > 1.25 volts. If, after the initial start up period, this pin is below 1.25V for 4 consecutive clock cycles after SSC > 3V then the circuit will shutdown. UVLO feedback pin. If this pin is above 1.5V then the OUTA pin is allowed to switch, if below 1.25V then OUTA is disabled. Drives one of the external NFETs, opposite phase of OUTAPB. Drives one of the external NFETs, opposite phase of OUTC. Drives the high side PFET. Battery input. This is the positive supply for the OUTA driver. Brightness polarity control. When this pin is low the CCFL brightness increases as the voltage at the BRIGHT pin increases. When this pin is high the CCFL brightness decreases as the voltage at the BRIGHT pin increases. Regulated 5V supply input. Sets the dimming cycle frequency. Usually about 100Hz. Negative input of the voltage control loop error amplifier. Output of the voltage control loop error amplifier. Brightness control input. A DC voltage on this controls the duty cycle of the dimming cycle. This pin is compared to a 3V ramp at the CT1 pin. Soft start ramp for the voltage control loop. (20uA source current.) The voltage at SSV clamps the voltage at COMP to be no greater than SSV thereby limiting the increase of the switching duty cycle. Drives the base of an external PNP transistor used for the 5V LDO. 11 CSDET 12 13 14 15 16 BATTFB OUTC OUTAPB OUTA VBATT 17 BRPOL 18 19 20 21 VDD CT1 FB COMP 22 BRIGHT 23 SSV 24 PNP 3 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Ordering Information AME9002 x x x x x Special Feature Number of Pins Package Type Operating Temperature Range Pin Configuration Pin Configuration Operating Temperature Range Package Type Number of Pins Special Feature A: 1 . 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. 13. 14. 15. 16. 17. 18. 19. 20. 21. 22. 23. 24. VREF CE SSC RDELTA FAULTB RT2 VSS OVPH OVPL FCOMP CSDET BATTFB OUTC OUTAPB OUTA VBATT BRPOL VDD CT1 FB COMP BRIGHT SSV PNP E: -40OC to 85OC J: SOIC (300 mil) P: Plastic DIP T: QSOP H: 24 Z: Lead free 4 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Ordering Information (contd.) Part Number AME9002AETH Marking AME9002AETH xxxxxxxx yyww AME9002AEPH xxxxxxxx yyww AME9002AEJH xxxxxxxx yyww Output Voltage N/A Package QSOP-24 Operating Temp. Range - 40oC to + 85oC AME9002AEPH N/A PDIP-24 - 40oC to + 85oC AME9002AEJH N/A SOIC-24 - 40oC to + 85oC n Absolute Maximum Ratings Parameter Battery Voltage (VBATT) ESD Classification Maximum 25 B Unit V Caution: Stress above the listed absolute maximum rating may cause permanent damage to the device n Recommended Operating Conditions Parameter Battery Voltage (VBATT) Ambient Temperature Range Junction Temperature Rating 7 - 24 - 40 to + 85 - 40 to + 125 Unit V o C C o n Thermal Information Parameter Thermal Resistance (QSOP - 24) Maximum Junction Temperature Maximum Lead Temperature (10 Sec) Maximum 325 150 300 Unit o C/W o C C 5 o AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Electrical Specifications TA= 25OC unless otherwise noted, VBATT = 15V, CT1 = 0.047uF, RT2 = 56K Parameter 5V supply (VSUPPLY) Output voltage Line regulation Load regulation Temperature drift 3.4V reference (VREF) Initial voltage Line regulation Temperature drift VREF V REFLINE V REFTC Vbatt = 15V, Iref = 0 7< Vbatt < 24V -10C 6 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Electrical Specifications(contd.) TA= 25OC unless otherwise noted, VBATT = 15V, CT1=0.047uF, RT2 = 56K Parameter Output A (OUTA) Peak current Output Low Voltage Output High Voltage Other outputs (OUTAPB, OUTC) Peak current Output Low Voltage Output High Voltage Soft start clamps (SSC, SSV) Initial SSC current Normal SSC current SSV current Other parameters CE high threshold CE low threshold OVPH threshold OVPL threshold CSDET threshold FCOMP charging current BATTFB high threshold BATTFB low threshold Average supply current Average off current Symbol Test Condition Min Typ Max Units IPEAKA VOL VOH 0.2mA -5mA 14.4 1 10.55 Amp V V IPEAKBC VOL VOH ISINK = 10mA ISOURCE = 10mA VDD - .7 1 0.25 Amp V V ISSCINIT ISSC ISSV 100 100 10 500 500 25 nA uA uA CE HIGH CELOW OVPHI OVPLO VTHCS IFCOMP V THBATHI VTHBATLO IBATT IOFF No FET gate current In the application 1.5 0.4 3.2 2.3 1.1 0.8 1.4 1.15 2.5 1 3.55 2.7 1.4 1.2 1.6 1.35 6 10 V V V V V uA V V mA uA 7 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Block Diagram VBATT R4 2K Q1 REF 1 C2 1 To Chip Enable Logic CE 3.4V REF 2VOK CE 140 nA 140 A 1ST Later RES_SSC 3V BLANK 5V LDO PNP 24 SSV 2 23 RES_SSV BRIGHT C14 1000pF SSC 3 C3 0.039 VSupply R3 RDELTA 22 BRIGHTNESS Control VOLT. COMP 4 21 C8 47nF FAULTB FB 5 VCO RT2 RAMP CLK 1.5V 20 EA1 2.5V CT1 B 6 R2 56K A VSS R7 30K 19 Dimming RAMP CEN RES_SSC RES_SSV C4 0.047F VDD 7 3.3V Fault Logic 18 C7 4.7F BRPOL OVPH C R35 D16 8 2.5V RES_FCOMP 17 2.5V 1A VBATT HI=Reverse LO=Normal OVPL R36 9 STRIKE 7.5V FCOMP 16 C7 PWM RES_FCOMP CLK 1.25V NORM OUTAPB 10 R10 604 R9 249 C32 1F CSDET HS Driver OUTA 15 B 14 Q2 11 VBATT R40 60K R41 10K BATTFB 2bit Count A Q3-1 C 2 OUTC 12 1.5V 1.25V BAITOK 13 Q3-2 8 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Application Schematic Figure 2. Double Tube Application Schematic (7V < Vbatt < 24V) R1 2K 1 C2 1F 2 CE SSV 23 C14 1000p VREF PNP 24 Q1 3 VDD R3 15k 5 C3 0.047F 6 R2 40K 7 D17 8 C33 100p D16 R36 10 C32 2.2nF R45 1M 11 SSC BRIGHT 22 0.1F 4 RDELTA COMP 21 C8 47nF 20 R7 30K FAULTB FB RT2 CT1 19 C4 0.047F VSS VDD 18 HI=Reverse LO=Normal C7 4.7F OVPH BRPOL 17 9 OVPL VBATT 16 R40 60k FCOMP OUTA 15 Q2 T1 CSDET OUTAPB 14 Q3-1 Q3-2 R41 10k 12 BATTFB OUTC 13 R37 2meg R35 2meg R38 3k R36 3k R10 680 D23 D22 R40 7.5k C34 0.01u D21 D20 R9A 221 R9B 221 R42,43 10k VDD 9 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Application Notes Overview The AME9002 application circuit drives a CCFL (cold cathode fluorescent lamp) with a high voltage sine wave in order to produce an efficient and cost effective light source. The most common application for this will be as the backlight of either a notebook computer display, flat panel display, or personal digital assistant (PDA). The CCFL tubes used in these applications are usually glass rods that can range from several cm to over 30cm and 2.5mm to 6mm in diameter. Typically they require a sine wave of 600V and they run at a current of several milliamperes. However, the starting (or striking) voltage can be as high as 2000V. At start up the tube looks like an open circuit, after the plasma has been created the impedance drops and current starts to flow. The starting voltage is also known as the striking voltage because that is the voltage at which an arc "strikes" through the plasma. The IV characteristic of these tubes is highly non-linear. Traditionally the high voltage required for CCFL operation has been developed using some sort of transformer LC tank circuit combination driven by several small power mosfets. The AME9002 application uses one external PMOS, 2 external NMOS and a high turns ratio transformer with a centertapped primary. Lamp dimming is achieved by turning the lamp on and off at a rate faster than the human eye can detect, sometimes called "duty cycle dimming". These "on-off" cycles are known as dimming cycles. Alternate dimming schemes are also available. Steady State Circuit Operation Figure 1 shows a block diagram of the AME9002. Throughout this datasheet like components have been given the same designations even if they are on a different figure. The block diagram shows PMOS Q2 driving the center tap primary of T1. The gate drive of Q2 is a pulse width modulated (PWM) signal that controls the current into the transformer primary and by extension, controls the current in the CCFL. The gate drive signal of Q2 drives all the way up to the battery voltage and down to 7.5 volts below Vbatt so that logic level transistors may be used without their gates being damaged. An internal clamp prevents the Q2 gate drive (OUTA) from driving lower than Vbatt-7.5V. NMOS transistors Q3-1 and Q3-2 alternately connect the outside nodes of the transformer primary to VSS. These transistors are driven by a 50% duty cycle square wave at one-half the frequency of the drive signal applied to the gate of Q2. 10 Figure 3 illustrates some ideal gate drive waveforms for the CCFL application. Figure 4 and 5 are detailed views of the power section from Figures 1 and 2. Figure 5 has the transformer parasitic elements added while Figure 4 does not. Referring to Figures 4 and 5, NMOS transistors Q3-1 and Q3-2 are driven out of phase with a 50% duty cycle signal as indicated by waveforms in Figure 3. The frequency of the NMOS drive signals will be the frequency at which the CCFL is driven. PMOS transistor, Q2, is driven with a pulse width modulated signal (PWM) at twice the frequency of the NMOS drive signals. In other words, the PMOS transistor is turned on and off once for every time each NMOS transistor is on. In this case, when NMOS transistor Q3-1 and PMOS transistor Q2 are both on then NMOS transistor Q3-2 is off, the side of the primary coil connected to NMOS transistor Q3-1 is driven to ground and the centertap of the transformer primary is driven to the battery voltage. The other side of the primary coil connected to NMOS transistor Q3-2 (now "off") is driven to twice the battery voltage (because each winding of the primary has an equal number of turns). Current ramps up in the side of the primary connected to Q3-1 (the "on" transistor), transferring power to the secondary coil of transformer. The energy transferred from the primary excites the tank circuit formed by the transformer leakage inductance and parasitic capacitances that exist at the transformer secondary. The parasitic capacitances come from the capacitance of the transformer secondary itself, wiring capacitances, as well as the parasitic capacitance of the CCFL. Some applications may actually add a small amount of parallel capacitance (~10pF) on the output of the transformer in order to dominate the parasitic capacitive elements. When the PMOS, Q2, is turned off, the voltage of the transformer centertap returns to ground as does the drain of NMOS transistor Q3-2 (the drain of Q3-2 was at twice the battery voltage). Halfway through one cycle, NMOS transistor Q3-1 (that was on) turns off and NMOS transistor Q3-2 (that was off) turns on. At this point, PMOS transistor Q2 turns on again, allowing current to ramp up in the side of the primary that previously had no current. Energy in the primary winding is transferred to the secondary winding and stored again in the leakage inductance Lleak, but this time with the opposite polarity. The current alternately goes through one primary winding then the other. The duty cycle of PMOS transistor Q2 controls the amount of power transferred from the primary winding to the secondary winding in the transformer. Note that the CCFL circuit can work with PMOS transistor Q2 on con- AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 3. Idealized Gate Drive Waveforms Q2 Gate (OUTA) VBATT VBATT- 7.5V Q3-1 Gate (OUTAPB) 5V 0V 5V Q3-2 Gate (OUTC) 0V Figure 4. Power Stage Single Tube Components (Same component designations used throughout) Figure 5. Power Stage Single Tube Components with parasitic elements (Same component designations used throughout) VBATT OUTA D = 0-100% Vhi = Vbatt Vlo = Vbatt-7.5V F = fosc Q2 T1 VBATT OUTA D = 0-100% Vhi = Vbatt Vlo = Vbatt-7.5V F = fosc Q2 Lp OUTAPB D=50% Vhi = 5V Vlo = 0V F = fosc/2 Lp Q3-1 Q3-2 OUTC D=50% Vhi = 5V Vlo = 0V F = fosc/2 T1 OUTAPB D=50% Vhi = 5V Vlo = 0V F = fosc/2 Q3-1 1:N Q3-2 OUTC D=50% Vhi = 5V Vlo = 0V F = fosc/2 L leak Signals OUTC and OUTAPB are the inverse of each other. Cparasitic CCFL Signals OUTC and OUTAPB are the inverse of each other. CCFL D5 D4 To Control Circuitry R9+R10 D5 D4 To Control Circuitry R9+R10 11 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller stantly (i.e. a duty cycle of 100%), although the power would be unregulated in this case. Figures 6,7 illustrates various oscilloscope waveforms generated by the CCFL circuit in operation. These figures show that the duty cycle of the gate drive at Q2 decreases as the battery voltage increases from 9 V to 21 V (as one would expect in order to maintain the same output power). The first three traces in Figures 6 and 7 show the gate drive waveforms for transistors Q2, Q3-1, and Q3-2, respectively. As mentioned before, the gate drive waveform for transistor Q2 drives up to the battery voltage but down only to approximately 7.5 V below the battery voltage. The fourth trace (in Figures 6,7) shows the voltage at centertap of the primary winding (it is also the drain of PMOS transistor, Q2). This waveform is essentially a ground to a battery voltage pulse of varying duty cycle. When the centertap of the primary is driven high, current increases through PMOS transistor, Q2 as indicated by the sixth trace down from the top. In region I the drain current of Q2 is equal and opposite to the drain current of Q3-1 since the gate of Q3-1 is high and Q3-1 is on. In region III the drain current of Q2 will be equal and opposite to the drain current of Q3-2 (not shown). In region II when PMOS transistor Q2 is switched off, the current through this transistor, after an initial sharp drop, ramps back down towards zero. In Figures 6 and 7 the fifth trace down from the top shows the drain voltage of Q3-1. (The trace for NMOS transistor Q3-2, not shown, would be identical, but shifted in time by half a period.) The seventh trace down from the top shows the current through the NMOS transistor Q3-1, which is equal to the current in PMOS transistor Q2 for the portion of time that PMOS transistor Q2 is conducting (see region I, for example). As the current ramps up in the primary winding, energy is transferred to the secondary winding and stored in the leakage inductance Lleak (and any parasitic capacitance on the secondary winding). If the current in the NMOS transistor is close to zero when that NMOS transistor is turned off that means that the CCFL circuit is being driven close to its resonant frequency. If the circuit is being driven too far from its resonant point then there will be large residual currents in the transistors when they are turned off causing large ringing, lower efficiency and more stress on the components. So called "soft switching" is achieved when the MOS drain current is zero while the MOS is being turned off. The driving frequency and transformer parameters should be chosen so that soft switching occurs. Once PMOS transistor Q2 completes one on/off cycle, 12 it is repeated again with the alternate NMOS transistor conducting. This complementary operation produces a symmetric, approximately sinusoidal waveform at the input to the CCFL load, as shown by the bottom trace in Figures 6 and 7. The operation of the CCFL circuit can be divided into 4 regions (I, II, III, and IV) as shown in Figures 6 and 7. Figure 8-1 shows the equivalent transformer and load circuit model for region I. During region I, one of the primary windings is connected across the battery, the current in that winding increases and energy is coupled across to the secondary. No current flows in the other winding because its NMOS is turned off and its body diode is reverse biased. The drain of that NMOS stays at twice the battery voltage because both primary windings have the same number of turns and the battery voltage is forced across the other primary winding. Figure 8-2 shows the equivalent transformer and load circuit model for region II. During region II, the battery is disconnected from the primary winding. In this configuration, current flows through both of the primary windings. The current decreases very quickly at first then ramps down to zero at a rate that is slower than the current ramped up. The initial drop is due to the almost instantaneous change in inductance when current flow shifts from one portion of the primary winding to both portions of the primary. Figure 8-3 shows the equivalent transformer and load circuit model for region III. During region III, the primary winding opposite from the one used in region I is connected across the battery, increasing current in that primary winding but in a direction opposite to that of region I. Energy is coupled across to the secondary as in region I but with opposite polarity. No current flows in the undriven winding because its NMOS is turned off and its body diode is reverse biased. The drain of that NMOS stays at twice the battery voltage because both primary windings have the same number of turns and the battery voltage is forced on the other primary. Region III is, effectively, the inverse of region I. Figure 8-4 shows the equivalent transformer and load circuit model for region IV. During region IV, the battery is disconnected from the primary winding. In this configuration, current flows through both of the primary windings with opposite polarity to that in region II. The current decreases very quickly at first then ramps down to zero at a rate that is slower than the current ramped up. Once again, the initial drop is due to the effective change in inductance when current flow shifts from one portion of the primary winding to both portions of the primary. Region IV is effectively the inverse of region II. AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 6. Typical Waveforms VBATT=9V VBATT=9V Q2 Gate (OUTA) 1.5V 5V 0V 5V 0V VBATT 0V VBATT x 2 0 0 IMAX 0 IMAX Q3-1 Gate (OUTAPB) Q3-2 Gate (OUTC) Center tap (Q2 DRAIN) Q3-1 Drain IDQ2 IDQ3-1 ILAMP Region I Region II Region III Region IV Figure 7. Typical Waveforms VBATT=21V VBATT=21V Q2 Gate (OUTA) Q3-1 Gate (OUTAPB) 13.5V 5V 0V 5V 0V VBATT 0V 2 x VBATT 0V 0A Q3-2 Gate (OUTC) Center tap (Q2 DRAIN) Q3-1 Drain IDQ2 IDQ3-1 IMAX 0A IMAX ILAMP Region I Region II Region III Region IV 13 AME, Inc. AME9002 Figure 8-1. Region I ILEAK ary imin l Pre CCFL Backlight Controller Figure 8-2. Region II ILEAK Cparasitic I Load Cparasitic I Load Figure 8-3. Region III ILEAK I Cparasitic Load Figure 8-4. Region IV ILEAK I Cparasitic Load Figure 9. Steady State Dimming Waveforms (after initial start up period) 3V BRIGHT 0.5V 5V SSV OV 5V SSC 3V 3V OV "Blanked" Faults CSDET < 1.25V OVPL > 2.5V CT1 Ignore Respond Ignore Respond "Unblanked" Faults OVPH > 3.3V Always Respond to Over voltage Faults Tube Current (time not to scale) ~ 6ms 14 AME, Inc. AME9002 Driving the CCFL ary imin l Pre CCFL Backlight Controller Unlike modified Royer schemes for driving CCFLs the secondary winding of the AME9002 method is not designed to look like a voltage source to the CCFL lamp. The circuit acts more like a current source (or a power source). The voltage at the transformer secondary is primarily determined by the operating point of the CCFL. The circuit will increase the duty cycle of Q2 thereby dumping more and more energy across to the secondary tank circuit until the CCFL tube current achieves regulation or one of the various fault conditions is met. There are two major modes of operation of the AME9002. The start up mode consists of the time from intial power up until the tube strikes or 1 second elapses. The steady state mode consists of operation that occurs after the start up mode finishes. The start up mode is useful for coaxing old or cold tubes into striking. It is believed that as a tube ages it becomes more and more difficult to strike an arc through the gas. Cold temperatures make this problem even worse. The AME9002 will allow higher than normal operating voltages across the CCFL for a period of up to one second in order to facilitate strking. This feature should extend the usable life of the CCFL as well as simplifying start up for "problem" applications. Start Up Mode When the circuit is first powered up or the CE pin transitions from a low to a high state a special mode of operation, known as the "start up mode", is initiated that will last for a maximum of one second. The exact duration of the start up period is determined by capacitor C3 on the SSC pin. Figure 10 shows a flow chart of the CCFL ignition sequence described here. The start up mode will end when one of two conditions is met: a) The CCFL strikes and the current sense voltage at the CSDET pin rises above 1.25V. b) The one second time period ends without the tube being struck, in this case the circuit will shut down. On the first cycle after power on (or a low to high transition on CE) C3 is initially discharged and the voltage on SSC is zero. It is charged up by a 140nA current source. When the voltage on C3 reaches 3 volts the start up mode has ended. A value of 0.39uF for C3 nominally yields a one second start up period. If the one second time period ends before the CCFL strikes then the circuit is shutdown until the user toggles the power supply or CE transitions from low to high again. In other words, if the CCFL successfully starts up then the start up time period will end before the one second time period is up. The SSC pin and C3 are also used to set the blanking period during steady state operation. This operation is described more completely below. At the beginning of the start up period capacitor C32, connected to FCOMP, is also discharged and the voltage at FCOMP is zero. The voltage at FCOMP controls the frequency at which the FETs are driven. When FCOMP is zero the frequency is at its maximum value. When FCOMP reaches 5V then the switching frequency is at its minimum value. The exact relation between the voltage at FCOMP and oscillator frequency is described more fully in the detailed description of the oscillator circuitry. At the beginning of start up mode FCOMP is zero volts so the switching frequency is at its maximum value. It is intended that this maximum frequency is significantly above the resonant frequency of the tank circuit made up of the transformer and CCFL load. In this way the voltage at the CCFL is lower than would be expected if the circuit was driven nearer to its resonant frequency. At this point in the operation of the circuit we assume that the CCFL has not struck and therefore appears as an open circuit to the transformer. After the tube has struck the voltage at the transformer output is controlled by the IV relationship of the CCFL. Without the variable frequency drive available with the AME9002 the user is unable to control the voltage across the CCFL before the CCFL strikes and current starts flowing in the CCFL. Capacitor C32 is charged by a 1uA current source with the following conditions: a) If OVPL < 2.5V the charging current is 1uA and the voltage at FCOMP ramps positive. b) If OVPL > 2.5V and OVPH < 3.3V then the charging current is zero and the voltage at FCOMP remains the same. c) If OVPH > 3.3V then FCOMP is discharged to approximately 1V, SSV is also driven to VSS. These conditions allow the voltage across the CCFL to be controlled during the start up period. The two thresholds available at OVPL and OVPH allow the user to tailor the start behavior for particular tubes. In Figure 11, initially SSV=SSC=FCOMP= zero volts. The switching duty cycle is zero, the switching frequency is maximum and the one second time period ramp has just started. The SSV ramps positive which 15 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 10. Ignition Flow Chart START Start 1 second timer F=Fmax Set SSV = 0V Yes No V(OVPH)> 3.3V No V(OVPL) > 2.5V Yes Timer End? Yes Yes V(OVPL) > 2.5V No Shutdown No Yes V(CSDET) < 1.25V Timer End? Yes V(CSDET) < 1.25V (after normal blanking and for 4 clk cycles) Yes No No No No F > Fmin? F > Fmin? No Yes F(new)=F(old) - delta Yes F(new)=F(old) - delta 16 Start Up Side ------- | ------ Steady State Operation Side AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 11. Start Up and Steady State Waveform 3V BRIGHT * CT1 ** 1.25V CSDET 5V VBATTOK VDDOK } VALID OVPH>3.3V <3V BLANK BLANK SSC F = fMIN F = fMIN <1 Sec FCOMP OVPL<2.5V OVPH<3.3V OVPL>2.5V OVPH < 3.3V OVPL OVPL>2.5V <2.5V OVPH < 3.3V OVPL<2.5V OVPH<3.3V ~ 6mS SSV < Initial Start Up Period> IF: OVPL<2.5V OVPH<3.3V THEN: FCOMP ramps up Frequency decreases FCOMP constant Frequency constant F COMP = V Frequency = FMAX SSV=0V COMP=0V Tube has struck and initial start period has ended. IF: OVPH > 3.3V THEN: Immediate shutdown OVPL>2.5V OVPH < 3.3V OVPH>3.3V OVPL > 2.5V during blanking period: nothing after blanking period: shutdown CSDET < 1.25V for 4 consecutive clock cycles during blanking period: nothing after blanking period: shutdown CSDET > 1.25V * BRPOL is Low ** Time axis is not to scale 17 AME, Inc. AME9002 ary imin l Pre Steady State Mode CCFL Backlight Controller allows the switching duty cycle to increase which, in turn, increases the voltage across the CCFL. At some point later SSV=5 volts, SSC and FCOMP are still ramping up. The tube voltage continues to increase, the switching duty cycle is no longer limited by SSV and is able to go to 100%, if indicated by the error amp loop. The switching frequency continues to decrease forcing the tube voltage higher. If the CCFL voltage is high enough so that OVPL > 2.5V (OVPL senses the CCFL voltage through a resistor or capacitor divider) then FCOMP stops increasing and the frequency remains constant. The frequency will remain constant until: OVPL < 2.5V OR.... OVPH > 3.3V (see below) OR...... The one second time period runs out and the circuit shuts down. If the voltage across the tube increases enough so that OVPH > 3.3V (as sensed through a resistor or capacitor divider) then FCOMP is pulled low (~1V), the switching frequency is increased, SSV is pulled low and the switching duty cycle goes to zero. It will remain in this state until: OVPH < 3.3V OR.... The one second time period runs out and the circuit shuts down. Ideally, during one of these states, the CCFL will strike, current will flow in the CCFL and the circuit will move from the start up mode into the steady state mode. Once an arc has struck, as sensed by CSDET > 1.25 volts, then the circuit will drive the CCFL at 100% brightness for approximately two dimming cycles (dimming cycles are on the order of 6mS as determined by the capacitor on CT1) in order to ensure that the CCFL is really "on". After those two full brightness dimming cycles the normal duty brightness control takes over, alternately turning the CCFL on and off at a duty cycle determined by the voltage at the BRIGHT pin. Remember, the circuit will only "try" to turn on for one second, after that point it gives up and shuts down. 18 At the beginning of each dimming cycle (after the start up mode) there is initially no arc struck in the CCFL. The CCFL load looks like an open circuit. (However an arc has been struck successfully in the start up mode so we assume the gas has "warmed up" and is ready to strike an arc again.) SSV is pulled to zero volts then ramps to 5 volts allowing the duty cycle of the switches to slowly increase to its steady state value. The voltage across the CCFL will increase with each successive clock cycle. Two events may then happen: 1) The gas inside the CCFL will ionize, the voltage across the CCFL will drop, the current through the CCFL will increase, and a stable steady state operating point will be reached. OR.... 2) One of the three fault conditions will be met that shut down the circuit (see Figure 11): a) The CCFL tube voltage continues to rise until the OVPH pin is higher than 3.3V at which point the circuit will shut down (immediately). b) The CCFL tube voltage continues to rise until the OVPL pin is higher than 2.5V at which point the circuit will shut down (except during the blanking interval). c) The CCFL current fails to rise high enough to keep the undercurrent threshold at the CSDET pin from tripping (for 4 consecutive clock cycles). Note that condition a) can be met at any time while the AME9002 is in steady state operation (after the start up mode). Condition b) can only be met after the SSC pin has risen above 3V (after blanking interval). Condition c) can only be met after the SSC pin has crossed 3V (after blanking interval) AND four successive undercurrent events occur in a row (CSDET < 1.25V). The SSC pin is pulled to VSS everytime the lamp is turned off, whether for a dimming cycle, user shutdown or fault occurrence. It ramps up slowly depending on the size of capacitor C3 connected to the SSC pin. The period of time when the b) and c) fault checks are disabled is called the "blanking" time. The blanking time occurs from the time SSC is pulled to VSS until it reaches 3V. See Figure 9 for some idealized waveforms illustrating the behavior just described. Control Algorithm There are 2 major control blocks (loops) within the IC. The first loop controls the duty cycle of the driving waveform. It senses the CCFL current (Figure 1 or 2, resistor R9 and R10) rectifies it, integrates it against an internal AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller reference and adjusts the duty cycle to obtain the desired power. This loop uses error amplifier EA1 whose negative input is pin FB and whose output is COMP. The positive input of EA1 is connected to a 2.5V reference. External components, R7 and C8, set the time constant of the integrator, EA1. In order to slow the response of the integrator increase the value of the product: (R7 X C8). The second control block adjusts the brightness by turning the lamp on and off at varying duty cycles. Each time the lamp turns on and off is referred to as a "dimming cycle". At the end of each dimming cycle the SSV pin is pulled low, this forces COMP low as well due to the clamping action of Clamp1 shown in Figure 1. At the beginning of a new dimming cycle COMP tries to increase quickly but it is clamped to the voltage at the SSV(softstart voltage) pin. A capacitor on the SSV pin (C8, Figure 1), which is discharged at the end of every dimming cycle, sets the slew rate of the voltage at the SSV pin, and hence also the maximum positive slew rate of the COMP pin. ["Dimming cycle" is explained more fully below] The BRIGHT, CT1 and BRPOL pins A user-provided voltage at the BRIGHT pin is compared with the ramp voltage at the CT1 pin (See Figure 12). If BRPOL is tied to VSS then as the voltage at BRIGHT increases the duty cycle of the dimming cycle and the brightness of the CCFL increase. If BRPOL is tied to VDD then the brightness of the CCFL diminishes as the BRIGHT voltage increases. The frequency of the dimming cycles is set by the value of the capacitor at pin CT1 (C4 in Figure 1 and 2) and it is also proportional to the current set by resistor R2. Setting C4 equal to 0.047uF and R2 equal to 47.5k yields a dimming cycle frequency of approximately 125Hz. The frequency should vary inversely with the value of C4 according to the relation: Frequency(Hz) = 1/[4 X R2 X C4] The brightness may also be controlled by using a variable resistor in place of R10 (See Figure 13). In this case the BRIGHT pin should be pulled to VDD so that the CCFL remains on constantly. This method can lead to flicker at low intensities but it is easy to implement. Harmonic distortion may also increase since the duty cycle of the waveform at the gate of Q2 will vary greatly with brightness. When using burst brightness control the duty cycle of the driving waveforms should not vary because the CCFL is running at 100% power or it is turned off. As long as the battery voltage does not change the duty cycle of the driving waveform also does not change greatly. This means that harmonic distortion can be minimized by optimizing the frequency and transformer characteristics for a particular duty cycle rather than a large range of duty cycle. 19 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 12. Duty Cycle Dimming Outside Chip Inside Chip BRPOL BRIGHT CHOP + - Brightness control voltage CT1 CHOP causes the CCFL to turn on and off periodically. 3V C4 50mV + + S Q R Figure 13. Alternative Brightness Control Inside Chip Outside Chip BRPOL T1 BRIGHT CHOP Always Hi + CT 5V This method disables duty cycle dimming - K Maximum current= R1//(2R+R) COMP K Minimum current= (R1+R2)//(2R+R) To PWM Comparator EA1 2.5V + FB RF R2 R1 2R R-C-D optional network + To Fault Control Logic - CSDET R 1.25V 20 AME, Inc. AME9002 RT2, RDELTA pin ary imin l Pre CCFL Backlight Controller The frequency of the drive signal at the gate of Q2 is determined by the VCO shown in Figure1. A detail of the VCO is shown in Figure 14. The user sets the minimum oscillator frequency with the resistor connected to pin RT2 (R2 in the figures). The relation is: Frequency (Hz) = 2.8E9 / R2 (ohms) You can see from the formula that as R2 is increased the frequency gets smaller. Resistor R3 controls how much the oscillator frequency increases as a function of the voltage at FCOMP. The relationship is: Delta frequency (Hz) = 3.44E8 * (5 - V(FCOMP)) / R3 You can see from the formula that the frequency will decrease as the FCOMP voltage increases. The amount of this increase is set by R3. The current in R3 decreases as the voltage at FCOMP increases and hence decreases the charging current into the timing capacitor of Figure 14 thereby decreasing the oscillator frequency. Supply voltage pins, VDD and PNP Most of the circuitry of the AME9002 works at 5V with the exception of one output driver. That driver (OUTA) and its power pad (VBATT) must operate up to 24V although the OUTA pad may never be forced lower than 8 volts away from the VBATT pin. The OUTA pin is internally clamped to approximately 7.5 volts below the Vbatt pin. The AME9002 uses an external PNP device to provide a regulated 5V supply from the battery voltage (See Figure 15). The battery voltage can range from 7V< VBATT < 24V. The PNP pin drives the base of the external PNP device, Q1. The VDD pin is the 5V supply into the chip. A 4.7uF capacitor, C7, bypasses the 5V supply to ground. If an external 5V supply is available then the external PNP would not be necessary and the PNP pin should float. When the CE pin is low (<0.4V) the chip goes into a zero current state. The chip puts the PNP pin into a high impedance state which shuts off Q1 and lets the 5V supply collapse to zero volts. When low, the CE pin also immediately turns PMOS transistor Q2 off, however transistors Q3-1 and Q3-2 will continue to switch until the 5V has collapsed to 3.5V. By allowing the Q3 transistors to continue to switch for some time after Q2 is turned off the energy in the tank circuit is dissipated gradually without any large voltage spikes. The VDD voltage is sensed internally so that the switching circuitry will not turn on unless the VDD voltage is larger than 4.5V and the internal reference is valid. Once the 4.5V threshold has been reached the switching circuitry will run until VDD is less than 3.5V (as mentioned before). Output drivers (OUTA, OUTAPB, OUTC) The OUTAPB and OUTC pins are standard 5V CMOS driver outputs (with some added circuitry to prevent shoot through current). The OUTA driver is quite different (See Figure 16). The OUTA driver pulls up to VBATT (max 24V) and pulls down to about 7.5 volts below VBATT. It is internally clamped to within 7.5V of VBATT. On each transition the OUTA pad will sink/source about 500mA for 100nS. After the initial 100ns burst of current the current is scaled back to 1mA(sinking) and 12mA(sourcing). This technique allows for fast edge transitions yet low overall power dissipation. Fault Protection, the OVPH, OVPL and CSDET pins During the startup mode the AME9002 does not actually sense for fault conditions, instead it uses the voltages at OVPL and OVPH to adjust the operating frequency for a smooth start up. The startup itself (or "strike") is detected when the voltage at CSDET rises above 1.25V. There are no voltages at OVPL, OVPH or CSDET that can cause a fault during the start up mode. During steady state operation the AME9002 checks for 3 different fault conditions. There are two overvoltage conditions and one undercurrent condition that can cause a fault. When any one of the fault conditions is met then the circuit is latched off. Only a power on reset or toggling the CE pin will restore the circuit to normal operation. (See Figure 17 for a schematic of the FAULT circuitry.) The first fault condition check can be used to detect overvoltages at the CCFL. Specifically, if the OVPH pin is above 3V then this fault condition is detected. The first fault condition is always enabled, there is no blanking period (except, of course, during the start up period when fault detection is disabled). The second fault condition checks that the voltage at OVPL is below 2.5V. This protection is disabled while the SSC ramp is below 3V such as during the beginning of every dimming cycle. Again, this check is disabled during the start up period like all the fault checks. 21 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller In order to enable the first two fault condition checks then the OVP pin must, indirectly, sense the high voltage at the input of the CCFL. The actual CCFL voltage must be reduced by using either a resistor or capacitor divider such that in normal operation the voltage at OVPL is lower than 2.5V and the voltage at OVPH is lower than 3.3V. The third fault condition check can be used to monitor the CCFL current. Specifically, it checks whether the voltage at the CSDET pin is higher than 1.25V. If CSDET does not cross its 1.25V threshold once during 4 successive clock cycles then this fault will be triggered. This protection is disabled while the SSC ramp is below 3V, such as at the beginning of every dimming cycle. This fault check is disabled during the start up mode, as are all the fault checks. This fault condition is used to check that a reasonable minimum amount of current is flowing in the tube. Figure 17 is a simplified schematic of the fault protection circuitry used in the AME9002. Most of the signals have been previously defined however some need a little explanation. The VDDOK signal is a power OK signal that goes high when the 5V supply (VDD) is valid. The CHOP signal stops the operation of the switching circuitry once every dimming cycle for burst mode brightness control. The output signal, FIRST, is high during the start up mode then is low during subsequent cycles. It causes the SSC pin to initially source 1000 times less current than on subsequent dimming cycles in order to provide the 1 second initial start up period. The NORM signal is an enable signal to the switching circuitry. When it is high the circuit works normally. When it is low the switching circuitry stops. SSC and SSV pins Besides defining the initial 1 second start up period the SSC pin's primary role is to define a time period in which the 2nd and 3rd fault condition (previously described) are disabled. This period of time is called the blanking interval. During the initial start up period after a power on reset or just after a low to high transition on the CE pin the SSC pin sources 140nA into an external capacitor, C3. For subsequent dimming cycles the SSC pin sources 140uA. During steady state operation the blanking interval is defined as the time during which V(SSC) < 3V. Once the voltage at SSC crosses 3V the blanking interval is finished and all three fault condition checks are enabled. (The OVPH > 3.3V fault check is always enabled after the initial start up period.) At the 22 beginning of the next dimming cycle the SSC pin is pulled to VSS then allowed to ramp upwards again. During steady state operation the SSV pin (like the SSC pin) is pulled to ground at the beginning of every dimming cycle then sources 20uA into an external capacitor. This creates a 0 to 5 volt ramp at the SSV pin. This ramp is used to limit the duty cycle of the PWM gate drive signal available at the OUTA pin. The SSV pin accomplishes duty cycle limiting by clamping the COMP voltage to no higher than the SSV voltage. Because the magnitude of the COMP voltage is proportional to the duty cycle of the PWM signal at OUTA the duty cycle starts each dimming cycle at zero and slowly increases to its steady state value as the voltage at SSV increases. (Figure 9 shows this operation.) During the initial start up mode the SSV pin starts at zero volts and ramps up to 5V just as in steady state operation. However, during the start up mode, if OVPH > 3.3V then SSV is pulled to VSS and only allowed to ramp up when OVPH < 3.3V. This action sets the duty cycle back to 0 volts then allows the duty cycle to increase as the SSV voltage increases. This type of duty cycle limiting is commonly called "soft-start" operation. Soft start operation lessens overshoot on start up because the power increases gradually rather than immediately. Unlike the SSC pin the current sourced by the SSV pin remains approximately 20uA during ALL dimming cycles. BATTFB The BATTFB pin is designed to sense the battery voltage and enable the pin OUTA. When the voltage at BATTFB is below 1.25 volts then OUTA is disabled, when the voltage at BATTFB is larger than 1.5V then OUTA is enabled. There is 250mV of hysteresis between the turn on and the turnoff thresholds. This pin does not disable any other portion of the circuit except the OUTA pin. Notably, the other two drivers, OUTAPB and OUTC continue to switch when the voltage at BATTFB is below 1.25V. Ringing Due to the leakage inductances of transformer T1 voltages at the drains of Q3 can potentially ring to values substantially higher than the ideal value (which is twice the battery voltage). The application schematic in Figure 17 uses a snubbing circuit to limit the extent of the ringing voltage. Components C9,R8,D2 and D3 make up the AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller snubbing circuit. The nominal voltage at the common node is approximately twice the battery voltage. If either of the drains of Q3 ring above that voltage then diodes D2 or D3 forward bias and allow the ringing energy to charge capacitor C9. Resistor R8 bleeds off the extra ringing energy preventing the voltage at the common node from increasing substantially higher than twice the battery voltage. The extra power dissipation is: P(dissipated) = Vbatt2 / R8 For the example, in Figure 17, the power dissipation of the snubber circuit with Vbatt=15V is 58mW or approximately 1% of the total input power. The value of R8 can be optimized for a particular application in order to minimize dissipated power. Excessive ringing is usually a sign that the driving frequency is not well matched to the resonant characteristics of the tank circuit. In a well designed application a snubber circuit will not be necessary. Layout Considerations Due to the switching nature of this circuit and the high voltages that it produces this application can be sensitive to board parasitics. In fact, one of the advantages, of this design is that the circuit uses the parasitic elements of the application as resonant components, thus eliminating the need for more added components. Particular care must be taken with the different gounding loops. The best performance has been obtained by using a "star" ground technique. The star technique returns all significant ground paths back to the center of the "star". Ideally we would place the center of the star directly on the VSS pin of the AME9002. The bypass capacitors would, ideally, be connected as close to the center of the star as possible. The schematic in Figure 18 attemps to show this star ground configuration by bringing all the ground returns back to the same point on the drawing. Separate ground returns back to the star are especially important for higher current switching paths. 23 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 14. VCO Detail 1A Vco_Control VDD 0 I_in R3 VDD RDELTA 2.5V OVPL 50:1 curent divider I_out 1.5V RT2 R2 VSS + - 0 RAMP 3.0V + - FCOMP C32 1F OVPH 3.3V CLK SSV Inside chip Outside chip Figure 15. LDO Detail Inside Chip Outside Chip PNP 1 R4 Q1 VBATT VDDOK 2 - To Fault Logic VDD 27 < VBATT < 24 + EN 2.5V Start UP CE To user enable circuitry C7 4.7F 24 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 16. OUTA Driver Circuitry Inside Chip Vbatt Outside Chip BV=5V BV=4V BV=7.5V OUTA PWM SIGNAL External PMOS, Q2 100nS 100nS 1mA 25 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 17. Fault Logic CE VDD VDDOK POR BATTFB 1.25V + - CLK FAULTB 1.25V CSDET OVPL 2.5V SSC 3.0V OVPH 3.3V + - RES 2Bit Counter Q L1 L2 S Q NORM R + - BLK_CS BLNK CHOPOUT + - S Q SSV R S Q + - L3 FIRST R VDDOK EN RES Q CT1 C4 Dimming Oscillator 2 Bit Shift D VDD BRIGHT BRPOL FCOMP + CHOPIN 26 AME, Inc. AME9002 Application Component Description ary imin l Pre CCFL Backlight Controller Figure 18 shows one typical application circuit for driving 4 tubes. Similar component designations are used on similar components both in figure 2 and Figure 18 as well as throughout this application note. R1 - Weak pull up for the chip enable (CE) pin. The voltage at CE will normally rise to 5 volts for a 12V supply. Pull down on the CE node to disable the chip and put it into a zero Idd mode. If the user wishes to drive node CE with 3.3 or 5.5 volt logic then R1 is not necessary C1 - This capacitor acts to de-bounce the CE pin and to slow the turn on time when using R1 to pull up CE. This can be useful when the battery power is disconnected from the circuit in order to turn the circuit off, when the battery is reconnected the chip does not immediately turn on which allows the battery voltage to stabilize before switching starts. If the user is actively driving the CE pin then the C1 capacitor may not be necessary. R3 - This resistor connected to the RDELTA pin determines how much the oscillator frequency will change with battery voltage. The relation, which is found earlier in the text, is: Delta frequency (Hz) = 3.44e8 * (5 - V(FCOMP)) / R3 C2 - This 1uF capacitor bypasses and stabilizes the internal reference C3 - This capacitor determines the length of the blanking interval at the beginning of every dimming cycle. At the end of every dimming cycle this capacitor is discharged to VSS then allowed to charge up at a rate controlled by its internal current source and C3. When the voltage on C3 (pin SSC) crosses 3 volts the blanking interval is over and all fault checks are enabled. The charging current into C3 (out of pin SSC) is normally 140uA but for the very first cycle after the chip is enabled the current is only 140nA, this determines the duration of the intial start up period (nominally 1 second) and is given by the relation: T(seconds) =( C3) * (3volts) / (140e-9amps) And for subsequent dimming cycles the blanking interval is: T(seconds) = (C3) * (3volts) / (140e-6amps) R2 - R2 sets the frequency of the oscillator that drives the FETs. The relation between R2 and frequency, that was found previously in the text, is: Frequency (Hz) = 2.8e9/R2 R2 = 56K yields approximately 50khz Note: that this is the frequency of the NMOS(Q3) gate drive. The PMOS(Q2) gate drive is exactly twice this value. R4 - This resistors pulls the base of Q1 up to Vbatt. Coupled with Q1 and C7 it is part of the 5V regulator that supplies the working power to the AME9002. When the PNP pin is turned off the base of Q1 is pulled high through R4, turning off Q1 and allowing the voltage at the VDD node (VSUPPLY) to decay towards zero. Q1 - This common PNP transistor (2n3906 is adequate) forms part of the 5V linear regulator which supplies power to most of the AME9002. R6 - This resistor, together with adjustable resistor R20, form a resistor divider that divides the regulated 5V down to some lower voltage. That lower voltage is used to drive the BRIGHT pin which, in turn, determines the duty cycle of the the dimming cycles and therefore the brightness of the lamps. If the user is driving the BRIGHT pin with his/her own voltage source then R6 and R20 are not necessary. C6 - This capacitor bypasses the BRIGHT pin. A noisy BRIGHT pin can cause unwanted flicker. R20 - see description of R6 C14 - This capacitor sets the slope of the soft-start ramp on pin SSV. The voltage at SSV limits the duty cycle of the Q2 gate drive signal available at pin OUTA. The voltage at the COMP node is internally clamped to the SSV node. Therefore the C14 cap limits how fast SSV, and hence, COMP can increase. Limiting COMP's increase will limit the increase of the switching duty cycle thereby creating a "soft start" effect. The charging current out of SSV is approximately 20uA so the rate of change of the SSV voltage is: SSV(Volts/sec) = (20e-6amps) / C14 C5 - This is the main battery bypass capacitor. C4 - This capacitor sets the frequency of the dimming cycles according to the relation: 27 AME, Inc. AME9002 Dim Cycle Freq(Hz) = 1 / [(4) * (R2) * (C4)] ary imin l Pre CCFL Backlight Controller Note that the frequency is also a function of R2. So the frequency of the main oscillator and the frequency of the dimming oscillator are not independent. C7 - This capacitor is the load capacitor for the 5V linear regulator. As such it also bypasses the 5V supply and should be laid out as close to the AME9002 as possible. C8 - This capacitor, in combination with resistor R7, determines the time constant for the error amplifier (integrator) EA1. The integrator is the primary loop stabilizing element of the circuit. In general this application is tolerant of a large range of integrator time constants. Increase the (C8 X R7) product to slow down the loop response. R7 - see C8 D6 - This diode can catch any negative going spikes on the drain of Q2. This diode is NOT strictly necessary. This is NOT a freewheeling diode such as in a buck regulator. Since the primary windings are tightly coupled to each other the body diodes of Q3-1 and Q3-2 keep their own drains clamped to VSS as well as the drain of Q2. The spikes that diode D6 may catch are of short duration and small energy. Q2 - This is a PMOS device. By modulating its gate drive duty cycle the power into the transformer, and then into the load, can be controlled. The breakdown of this device must be higher than the highest battery voltage that the application will use. The peak current load is roughly twice the average current load. Q3-1, Q3-2 - These are NMOS devices. They are driven alternately with 50% duty cycle gate drive. The frequency of the gate drive is one half of the gate drive frequency of Q2. The gate drive is from 0 to 5 volts. The breakdown voltage of these devices must be at least twice the highest battery voltage. Peak current is roughly twice the average supply current. C9,R8,D2,D3 - These devices form a snubber circuit that can dissipate ringing energy. The snubber circuit is not strictly necessary. In fact a well designed circuit should not require these devices. (These elements were described in more detail earlier.) R9A, R10 - The sum of R9A and R10 sets the current 28 in one CCFL tube. As the sum of R9A and R10 decreases the tube current goes up, as the sum of R9A and R10 increase the tube current goes down. The RMS tube current is roughly: Irms = 6V / (R9A + R10) R9A and R10 also form a voltage divider that drives the CSDET pin. The purpose of the voltage divider is to keep the maximum voltage at CSDET under 5 volts under all conditions. The CSDET pin checks to see if there is any current in the CCFL. If the voltage at CSDET is larger than 1.25V once every clock cycle then the AME9002 assumes there is current in the CCFL and allows operation to continue. CSDET is also used to detect when the CCFL first strikes during the initial start up period. D4,D5 - These diodes rectify the current through the CCFL to provide a positive voltage for regulation by the error amplifier, EA1. The following components are only used for multiple tube operation: Q4,Q5 - These bipolar devices buffer the gate of Q2. That allows Q2 to be made much bigger without dissipating more power or increasing the cost of the AME9002. Q4 is an NPN transistor and Q5 is a PNP transistor. R35,R36,D16 etc. - These devices form a voltage divider and rectifier combination to sense higher than normal CCFL operating voltages. ( This operation is explained in more detail below.) You can diode "OR" as many of these divider/rectifier circuits as you have different CCFLs. Each time you add another double output transformer you must add another set of these resistors and diode networks. ( This operation is explained in more detail in the next section.) D20, D21, R42, R40 and C34 etc. - These devices are not strictly necessary for single tube operation. In single tube operation the junction of R9A and R10 can be directly fed into the CSDET pin. However for multiple tube operation these devices are necessary to allow for any one of the different tubes to be able to pull CSDET below 1.25V and allow a fault to be detected. Figure 1, a single tube application, has these devices included in order to facilitate the transition to multiple tube design as well as working quite well for the single tube application. AME, Inc. AME9002 Multiple Tube Operation ary imin l Pre CCFL Backlight Controller The AME9002 is particularly well suited for multiple tube applications. Figure19 shows the power section of a two tube application. The major difference between this application and the single tube application is the addition of another secondary winding on the transformer. The primary side of the transformer and its associated FETs are exactly the same as the single tube case although the FETs may need to be resized due to the increased current in two tube applications. The secondaries are wound so that the outputs to the CCFL are of opposite phase (see Figure 20) although this is not strictly necessary. When the voltage at one secondary output is high (+600 volts) the other secondary output should be low (-600 volts). The other secondary terminals are connected to each other. In a balanced circuit the voltage at the connection of the two secondaries will, ideally, be zero. Of course in a real application the voltage at the connection of the two secondaries will deviate somewhat from zero. The multi-tube configuration is modular. Since each double transformer can drive two CCFLs it is possible to construct 2, 4, 6..... tube solutions using the basic architecture. Of course the FETs must be properly sized to handle the increased current. Figure 21 shows a 4 tube application. In this configuration the common secondary connection (the node NOT connected to the lamp) is made with the opposite transformer. In this way the secondary current from the winding on the first transformer should be equal to the secondary current of its companion winding on the second transformer. In the case of 4 lamps driven by two transformers there are two sets of common secondary nodes. Sensing the current in the multiple tube case requires some extra circuitry. Normally the CSDET pin checks for the existence (or absence) of current in the CCFL. If current is detected then the initial start mode terminates and steady state operation begins. During steady state operation if no current is detected for 8 consecutive clock cycles then the circuit is shutdown. Since there is only one CSDET pin yet there are multiple tubes extra circuitry is required. Take the two tube case of Figure 19 for example. The current through the tube on the right hand side is regulated by the integrator made of R7, C8 and EA1. However, for purposes of fault detection and strike detection it is beneficial to monitor the current through both tubes. In this case R9B senses the current in the left tube in the same way R9A senses the current in the right hand tube. If the current through either tube is zero then R9A or R9B will try to pull node A or B to zero. Resistors R42 and R43 attempt to pull node A and B up but the value of R42 and R43 (nominally 10K) is much larger than the values of resistors R9A and R9B (nominally 221ohms) allowing node A and B to pull close to VSS when there is zero current in their respective CCFL tubes. The absence of current in either tube essentially pulls node A or B to VSS. In normal operation the voltage at nodes A and B should look like alternating, positive half sinusoids. (See figure 22.) If, however, there is no current flowing in one of the tubes then one half of the sinusoids would be missing and the voltage at CSDET would drop compared to its normal value. The values of the RC network made up of R4 and C34 are chosen so that the voltage at CSDET is always larger than 1.25 volts when both half sinusoids are present but is less than 1.25V when only one sinusoid is present. The concept can be applied to any even multiple of tubes. The tube without the current will dominate the voltage at CSDET so a failure in any single tube will cause the circuit to shutdown. In a similar manner, during start up all tubes must have current flowing in them before CSDET will rise above 1.25V and signal that the tubes have struck and that the initial start up mode is over. For every 2 extra tubes that need to be added the user must add one more transformer, and two resistor divider networks plus two diodes (R35, R36, R37, R38, D16, D17) to sense the CCFL voltage as well as two more diodes and two more resistors to sense the tube current (R9A, R9B, D20, D22). Resistors R42, R43, R40, diodes D21, D23 and capacitor C34 do not need to be replicated every time more CCFLs are added because they are shared in common on the CSDET node. Figure 18 shows a complete four tube schematic. Figure 21 shows a detail of the current and voltage sensing circuitry for the four tube application. Analogous components have been given the same numbers as in the single tube schematic. There is really very little difference between the the single tube configuration and the multitube version. Transistors Q4 and Q5 are added to buffer the high side drive OUTA. This may be necessary because the PMOS devices for larger current applications have larger gate drive requirements. The MOS transistors are sized bigger for the 4 tube application as would be expected. The peak currents are much higher so the Vbatt bypassing capacitor must be increased as well. The schematic shows C5 as a 100uF capacitor but higher values such as 220uF are not uncommon in order to minimize ripple on Vbatt. 29 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 18. Four Tube Application Schematic BATT R4 2K Q1 PNP 2N3906 1 Q4 NPN 2N3904 3 R8 C9 1uF Q2 5602 3.9k R1 1Meg Q5 PNP 2N3906 R6 SNUB 2, 4 D2 IN914 D3 IN914 BRIGHT 51k 10 10 3 3 4 9 4 9 T1 2XTRANS 12 12 2 2 5 7 5 7 T2 2XTRANS R3 15k LX C2 1uF U1 Vref 1 Vref 2 CE SSC RDELTA FAULTB RT2 VSS OVPH OVPL FCOMP CSDET BATTFB AME9002 PNP SSV BRIGHT COMP FB CT1 VDD VDD1 VBATT OUTA OUTAPB OUTC 24 23 22 21 20 19 18 17 16 15 14 13 CE C3 0.047uF R2 C1 0.1u R40 60K 40k 3 4 5 6 7 8 9 10 C8 47nF R7 VDD 30.1k R20 C14 1000p 100k Q3-1 IRFR3303 Q3-2 IN914 R10 680 R35 IRFR3303 D5 IN914 R37 R39 R51 D19 D18 D17 D16 R36 C6 0.1uF C7 4.7uF 303 D6 1N5819 R9A 221 R9B 221 R38 R9C 221 R50 R52 R9D 221 D4 OUT-1 C32 2200p 11 12 R41 10K C4 C5 + 0.047uF 100uF VDD D20 D21 D22 D23 D24 D25 D26 R42 10k R43 10k R40 7.5k C34 0.01u 30 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 19. Double CCFL Power Section VBatt OUTA Q2 T1 OUTB Q3-1 Q3-2 OUTC OVPL/OVPH R37 R38 R35 R36 OVPL/OVPH C8 Outside Chip D5 (B) R9B D22 D23 (C) D4 R10 (A) D21 D20 R9A R43 1.25V R7 FB EA1 COMP Inside Chip 2.5V CSDET To PWM Comparator R42 To Fault Logic VDD R40 C34 Figure 20. Double transformer construction detail Low voltages Secondary Primaries Secondary Large Positive (Negative) Voltage Large Negative (Positive) Voltage Common Core Low voltages in the center 31 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 21. Four Tube Power Section VDD R42 OUTA T2 R35 R36 R43 D26 R9D R37 Q2 VBatt R39 R50 D23 D22 R9C R38 D24 D25 R9B R51 OUTAPB Q3-1 T1 To R7 and C8 integrator OUTC Q3-2 R10 R9A D20 D21 D4 D5 R52 C34 R40 To OVPL OVPH To CSDET 32 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller Figure 22. Normal Operation (Filtered Voltage > 1.25V e No Fault) NODE A NODE B unfiltered 1.25 NODE C filtered One Tube Missing Operation (Filtered Voltage < 1.25V e Fault) NODE A NODE B No Current in TUBE B unfiltered 1.25 filtered NODE C 33 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Package Dimension QSOP24 Top View D SYMBOLS A A1 E1 E MILLIMETERS MIN 1.524 0.101 INCHES MIN 0.060 0.004 MAX 1.752 0.228 MAX 0.069 0.009 A2 b b1 c c1 D ZD E E1 L 1.473REF 0.203 0.203 0.177 0.177 8.559 0.304 0.279 0.254 0.228 8.737 0.058REF 0.008 0.008 0.007 0.007 0.337 0.012 0.011 0.010 0.009 0.344 Bottom View K 0.838REF 5.791 3.810 0.406 6.197 3.987 1.270 0.033REF 0.228 0.150 0.016 0.244 0.157 0.050 J L1 e J Side View ZD A2 A b e See Detail A 0.254BSC 0.635BSC 1.27REF 1.27REF 0o 5o 0o 0.33 x 45 8o 15 o o 0.010BSC 0.025BSC 0.050REF 0.050REF 0o 5o 0o 8o 15o - K e e1 e2 R A1 0.013 x 45 o End View Detail A b1 c 1 R c 2 L1 c1 (c) c L c (b) 34 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Package Dimension SOIC24 Top View SYMBOLS E H MILLIMETERS MIN MAX 2.65 0.30 2.31 0.51 0.32 15.60 7.60 INCHES MIN 0.092 0.004 0.089 0.013 0.009 0.598 0.291 MAX 0.104 0.012 0.091 0.020 0.013 0.614 0.299 A A1 Pin No.1 Indentifier 2.35 0.10 2.25 0.33 0.23 15.20 7.40 A2 B C Bottom View D E e H L 1.27BSC 10.00 0.40 0 o 0.050BSC 0.394 0.016 0 o 10.65 1.27 8 o 0.419 0.050 8o Side View D A2 e B A1 A End View Detail A C See Detail A c L 35 AME, Inc. AME9002 ary imin l Pre CCFL Backlight Controller n Package Dimension PDIP24 Top View R1.524 x 0.762 DP (R0.060 x 0.030") DP SYMBOLS C L E1 MILLIMETERS MIN MAX 6.35 4.95 0.56 1.77 0.39 32.70 15.87 14.73 INCHES MIN 0.015 0.125 0.014 0.030 0.008 1.154 0.005 0.600 0.485 MAX 0.250 0.195 0.022 0.070 0.015 1.287 0.625 0.580 A A1 A2 b b2 0.39 3.18 0.35 0.77 0.20 29.30 0.13 15.24 12.32 Side View D c 1 D1 A2 Base Plane Seating Plane C D D1 A L E E1 e eB L 1 2 A1 e b2 b 2.54BSC 15.24 2.93 7 7 o o 0.100BSC 0.600 0.115 7 o 17.78 5.08 0.700 0.200 End View (Outer to Outer) 7o E c 2 c eB 36 www.ame.com.tw E-Mail: sales@ame.com.tw Life Support Policy: These products of AME, Inc. are not authorized for use as critical components in life-support devices or systems, without the express written approval of the president of AME, Inc. AME, Inc. reserves the right to make changes in the circuitry and specifications of its devices and advises its customers to obtain the latest version of relevant information. (c) AME, Inc. , May 2004 Document: 2023-DS9002-B Corporate Headquarter AME, Inc. 2F, 302 Rui-Guang Road, Nei-Hu District Taipei 114, Taiwan, R.O.C. Tel: 886 2 2627-8687 Fax: 886 2 2659-2989 U.S.A.(Subsidiary) Analog Microelectronics, Inc. 3100 De La Cruz Blvd., Suite 201 Santa Clara, CA. 95054-2046 Tel : (408) 988-2388 Fax: (408) 988-2489 |
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